Frequency multiplying circuit

ABSTRACT

A silicon, monolithic, integrated-circuit, stereo multiplex receiver includes a 19 kc. doubler circuit responsive to the 19 kc. pilot signal present in the stereo multiplex composite signal received. The doubler circuit includes an NPN integrated circuit transistor amplifier connected to a 38 kc. LC tank circuit, with the base of the amplifier being supplied with the 19 kc. signals across a string of series connected integrated circuit transistors which provides logarithmic compression of the 19 kc. signals; so that the transistor amplifier is not driven into saturation. An RC filter circuit is connected to the emitter of the transistor amplifier, to provide a further degenerative backbias for the transistor aiding in preventing the driving of the transistor into saturation. The 38 kc. signals present on the collector of the transistor amplifier are supplied to a stereo demodulator circuit and the signal present at the emitter of the transistor amplifier is used as the input to a stereo lamp driver circuit.

United States Patent Primary Examiner-Donald D. Forrer Assistant Examiner-Harold A. Dixon Attorney-Mueller & Aichele ABSTRACT: A silicon, monolithic, integrated-circuit, stereo multiplex receiver includes a 19 kc. doubler circuit responsive to the 19 kc. pilot signal present in,the stereo multiplex composite signal received. The doubler circuit includes an NPN integrated circuit transistor amplifier connected to a 38 kc. LC tank circuit, with the base of the amplifier being supplied with the 19 kc. signals across a string of series connected integrated circuit transistors which provides logarithmic compression of the 19 kc. signals; so that the transistor amplifier is not driven into saturation. An RC filter circuit is connected to the emitter of the transistor amplifier, to provide a further degenerative back-bias for the transistor aiding in preventing the driving of the transistor into saturation. The 38 kc. signals present on the collector of the transistor amplifier are supplied to a stereo demodulator circuit and the signal present at the emitter of the transistor amplifier is used as the input to a stereo lamp driver circuit.

[72] inventors Gildo Cecchin Niles; James H. F eit, Chicago, both 01,111. [21] Appl. No. 797,008 [22] Filed Feb. 6, 1969 [45] Patented June 15, 1971 (73] Assignee Motorola, inc.

' Franklin Park, Ill.

[54] FREQUENCY MULTIPLYING CIRCUIT 12 Claims, 1 Drawing Fig.

[52] U.S.Cl 307/295, 307/271, 328/20. 333/14 [51] lnt.C1 ..H0b 19/00, [50] Field of Search H04b 3/04 328/16, 20,23,27, 151; 307/295, 271; 333/14 [56] References Cited UNITED STATES PATENTS 1,485,650 3/1924 Vennes 328/16 2,249,503 7/1941 Thompson. 328/20 2,414,541 1/1947 Madsen..... 328/16 2,579,217 12/1951 Tyzzer.... 328/16 2,861,182 11/1958 Green..... 328/145 3,089,968 3/1963 Dunn 328/145 'RF. AME CONVERTE 1. F. AMP LIMITER STEREO LAMP DRIVER FREQUENCY MULTIPLYING CIRCUIT BACKGROUND OF THE INVENTION The composite stereophonic signal transmitted for provid ing compatible monaural and stereophonic reception in PM receivers includes an audio summation signal of the left and right channels, known as the L+R signal, an amplitude modulated audio difference signal on a suppressed subcarrier, known as the I .R signal, and a continuous wave pilot signal which presently is of 19 kc. To demodulate the stereophonic signals, it is necessary to detect the 19 kc. signal and to double its frequency in order to provide the missing 38 kc. carrier which is the suppressed subcarrier for the L-R signals received by the FM stereophonic receiver.

Detection circuits are provided for detecting and separating the 19 kc. signal from the remainder of the signals received and for applying these 19 kc. signals to frequency doubler circuits, which in turn are used to operate stereophonic demodulator or matrixing circuits for producing the desired L and R output signals. Limiting of the 19 kc. signal is not normally required in a stereo multiplex demodulator as the 19 kc. level recovered from the detector in any one radio varies only due to drift of the FM detector, differences in 19 kc. modulating level at the transmitter, and under weak signal conditions when the IF drops out of limiting.

If, however, the multiplex demodulator is designed to operate with a number of different receiver designs, the 19 kc. level may vary depending on the characteristics of the radio. Consequently, 19 kc. limiting may be desirable to prevent other active stages from being overdriven. Limiting circuits however create a problem in home stereophonic receivers inasmuch as they cause the generation of higher order odd and even harmonics in the signals present in the receiver, and some of these harmonic signals combine with a background music channel broadcast by some stations. This background music channel extends approximately 7 kc. on either side of a 67 kc. subcarrier signal. It is generally referred to as the subsidiary communication authorization (SCA) signal or the store-cast signal. If this background music channel is present in the received signal, it is possible that the harmonics generated in the limiting of the 19 kc. signal may cause 57 kc. and 76 kc. signals in the regeneration process which in turn mix with the storecast" or SCA components to produce audio interference.

Thus it is desirable to provide for a regeneration circuit for producing the desired 38 kc. signal without generating harmonics which can combine with the storecast or SCA components to produce audio interference at the output of the receiver. In addition it is desirable to provide a stereophonic frequency doubling system in which the major portion of the system can be fabricated as part of an integrated circuit in order to effect the desirable savings of space and cost which are inherent in such devices.

SUMMARY OF THE INVENTION It is an object of this invention to provide an improved frequency doubler circuit.

It is an additional object of this invention to provide an integrated circuit frequency doubler circuit providing for logarithmic compression of the input signals applied to the doubler circuit in order to prevent overdriving of the doubler circuit.

In accordance with a preferred embodiment of this invention, signals, the frequency of which are to be multiplied, are supplied to the frequency multiplying circuit through a threshold detecting and logarithmic compression circuit, the output of which supplies the signals to the input of an amplifying device in the frequency multiplying circuit. The signal peaks are supplied to the amplifying device and the logarithmic compression prevents the amplifying device from being overdriven, so that undesirable harmonics are not generated, while at the same time permitting desirable limiting of the signal level. Additional self-biasing of the amplifying device further aids in the prevention of overdriving of the amplifying device.

BRIEF DESCRIPTION OF THE DRAWING The drawing shows a circuit diagram, partially in block form, of a preferred embodiment of a stereophonic multiplex receiver using a frequency multiplying circuit according to the invention.

DETAILED DESCRIPTION Referring now to the drawing, there is shown a stereophonic multiplex receiver including a frequency doubling circuit which is indicated as being part of an integrated circuit package enclosed by dotted lines in the drawing. A frequency modulated FM carrier wave containing the sum signal of the right and left audio signals and the difference signal of the right and left audio signals, amplitude modulated on a suppressed subcarrier wave, and a pilot signal having a frequency one-half that of the suppressed subcarrier frequency is received by an antenna 10 and is supplied to a receiver circuit 11. The circuit 11 represents the usual RF amplifier, converter, IF amplifier, and limiter which may be of known design. The output of the circuit 11 then is coupled to an FM detector circuit 12 the output of which supplies signals to a preamplifier 13 which is formed as part of the integrated circuit package.

If a composite stereo signal is being received by the receiving device shown in the drawing, the output of the preamplifier circuit 13 includes the 19 kc. pilot signal component; and this 19 kc. component is detected and separated in a 19 kc. signal separator circuit 15, the output of which is a 19 kc. signal which may be obtained in a suitable manner. In addition the output of the preamplifier circuit 13 contains the stereo left and right composite signals which are supplied over a lead 16 to a stereo demodulator circuit 17, which also is formed as part of the integrated circuit including the preamplifier l3 and the signal separator circuit 15. In order to separate the left and right signals in the stereo demodulator 17, it is necessary to provide the reconstructed 38 kc. carrier to the demodulator circuit 17 for synchronous demodulation of the stereophonic composite signal supplied to the demodulator over the lead 16.

In order to accomplish this reconstruction of the 38 kc. signal, the 19 kc. signal obtained from the output of the separator circuit 15 is fed to the base of an integrated circuit PNP transistor 21, the emitter and collector of which are connected to the collector and base respectively of an NPN transistor 22, forming the input to a frequency doubler circuit 20. This combination of the transistors 21 and 22 functions as a PNP amplifier and is used due to the fact that an integrated circuit PNP amplifier having suitable power handling characteristics is difficult to achieve with the present state of integrated circuit technology. As a consequence it is necessary to provide the NPN transistor 22 as the output for the PNP transistor 21. The collector of the transistor 22 is connected to a source of positive potential through a collector resistor 23, and the output load for the transistor 22 is in the form of a voltage reference string or threshold detector 25 consisting of four series-connected NPN transistors 26, 27, 28 and 29. It should be noted that the collector-emitter paths of these transistors are connected in series, and the bases ofeach of the transistors 2629 is connected to its respective collector. Thus, the transistors 26, 27, 28 and 29, which are fabricated on the integrated circuit chip, operate as diodes with signal varying from zero to forward bias when connected in the circuit between the emitter of the transistor 22 and ground as shown in the drawing.

The output signals developed at the emitter of the transistor 22 and applied across the string of transistors 25 are coupled to the base of an NPN transistor amplifier 30 which is the input amplifier for the 38 kc. doubler circuit 20. The connection is made to the base of the transistor 30 from the junction between the emitter of the transistor 22 and the collector of the transistor 26 and this junction also is connected to one end of a resistor 31, the other end of which is connected to the junction between the emitter of the transistor 27 and the collector of the transistor 28. The resistor 31 operates to establish an initial biasing potential on the base of the transistor amplifier 30 in the doubler circuit.

The transistors 26, 27, 28 and 29 operate so that they are relatively nonconductive until a voltage is applied across the string which exceeds the sum of the forward breakdown voltages of the transistors. When the voltage applied across the transistor string exceeds this initial threshold voltage, the transistors are biased into their forward conducting direction and exhibit relatively little increased voltage drop thereacross for increased current flowing through them since they operate as forward biased diodes in the circuit. As a consequence, the transistor string 25 provides a relatively constant voltage drop for signals in excess of the threshold value irrespective of the current passing through them; so that increased signal levels obtained from the output of the 19 kc. separator circuit result in increased voltage drops being present across the transistor 22 and the resistor 23, while the voltage drop across the transistor diode string 25 remains relatively constant.

This results in a logarithmic compression of the signals applied to the base of the transistor 30 which is rendered conductive only by signal peaks of the 19 kc. signal. The magnitude of these peaks, however, as applied to the base of the transistor 30, is relatively constant, irrespective of the mag nitude of the signal peaks obtained from the separator circuit 15 in excess of the threshold voltage of the string 25, since the excess energy of the signal peaks is dissipated by increased conduction through the series connected transistors 26, 27, 28 and 29. Thus. as the signal peaks applied to the transistors 21 and 22 continue to increase, the resulting increased current applied through the transistors 26, 27, 28 and 29 causes only slightly increased biasing potential to be applied to the base of the transistor 30. As a consequence, the output of the transistor 30 applied to a 38 kc. tank circuit 33 is relatively constant; and due to the fact that only the peaks of the 19 kc. signal are supplied to the transistor 30, sufficient even harmonies are present to cause the tank circuit 33 to resonate. Although four transistors 26-29 have been shown in the logarithmic compression circuit connected to the base of the transistor 30, the number of transistors used in the transistor string 25 may be varied to provide the desired amount of compression necessary to prevent overdriving of the input transistor 30, and may be more or less than the four transistors shown in the drawing.

In order further to insure against overdriving of the transistor 30, an RC filter circuit 35 is connected between the emitter of the transistor 30 and ground to establish a DC level which serves as a degenerative self-bias on the emitter of the transistor 30. When the transistor 30 is rendered conductive, the DC pulses present on its emitter are utilized to rapidly charge the capacitor in the circuit 35 to the DC level of the pulses. The resistor of the RC circuit 35 has a relatively high value of resistance, so that the discharge time for the capacitor exceeds the pulse rate at which the transistor 30 normally is driven into conduction. Thus, a DC voltage which is substantially equivalent to the peak DC signal obtained from the output of the transistor 30 is present at the junction of the emitter ofthe transistor 30 and the RC circuit 35; and as the output of the transistor 30 increases, this DC potential increases in value to back bias the emitter of the transistor 30 accordingly. This back bias functions to counteract the tendency of increased signals applied to the base ofthe transistor 30 from driving the transistor into saturation.

The signals present on the collector of the transistor 30 from the resonating tank circuit 33 are the desired 38 kc. subcarrier signals, and these signals are supplied to the demodulator circuit 17 to provide synchronous demodulation of the multiplex signals applied to the circuit 17 over the lead 16.

The output of the demodulator 17 is applied to a pair of left and right audio amplifiers l8 and 19, which in turn drive left and right speakers 38 and 39, respectively.

in addition to providing a self-bias for the transistor 30, the DC level obtained from the RC filter circuit 35 also is applied to a stereo lamp driver circuit 40 to provide an input signal level to the circuit 40 to cause an output to be obtained therefrom which is used to energize a stereo indicator lamp 41. The lamp driver circuit 40 generally is in the form a trigger circuit responsive to input voltages in excess of a predetermined level before it switches to a different stable state; so that whenever the DC level of the circuit 35 exceeds this input trigger level, the circuit 40 causes energization of the lamp 41.

The value of the capacitor in the filter circuit 35 is chosen to be large enough so that spurious or short time signals obtained from the output of the 19 kc. separator circuit are not sufficient to provide a high enough voltage level to trigger the lamp driver circuit 40. The signals must be present for a predetermined length of time which is chosen to be sufficient to indicate that a true stereophoni: reception is in fact present.

The 38 kc. signal obtained from the output at the collector at the transistor 30 is a symmetrical signal relatively free of higher order odd and even harmonics due to the fact that the transistor 30 is prevented from being overdriven. As a consequence the generation of harmonics which might mix with the storecase" signal components to produce undesirable audio interference is reduced to a minimum. This in conjunction with a synchronous demodulation technique makes it possible to eliminate the conventional storecase" filters used in such circuits, which is extremely desirable in an integrated circuit of the type indicated in the drawing.

We claim:

1. A frequency multiplying circuit including in combination;

a source of signals at a first frequency to be multiplied, said signals being subject to varying amplitude;

a resonant circuit tuned to a harmonic of said first frequena transistor having base, collector and emitter electrodes, the collector electrode being coupled with said resonant circuit;

first and second voltage supply terminals adapted to be connected across a source of DC potential;

means for coupling the collector electrode of said transistor with said first voltage supply terminal;

circuit means coupling the emitter of said transistor with said second voltage supply terminal;

semiconductor diode means connected between the base of said transistor and said second voltage supply terminal; and

means for applying signals from said source to the base of said transistor, said diode means operating to provide logarithmic compression of signals applied thereacross with an amplitude in excess of a predetermined magnitude to prevent driving said transistor into saturation.

2. The combination according to claim 1 wherein said semiconductor diode means includes a plurality of semiconductor diode junctions connected in series between the base of said transistor and said second voltage supply terminal, with said semiconductor diode junctions being forward biased by the peaks of signals at said first frequency which are in excess of the forward breakdown voltage of said semiconductor diode junctions interconnected between the base of said transistor and said second voltage supply terminal.

3. The combination according to claim 2 further including a resistor coupled to the base of said transistor in parallel with at least one of said semiconductor diode junctions.

4. The combination according to claim 1 further including an energy storage device connected between the emitter of said transistor and said second voltage supply terminal, said energy storage device storing energy during the periods when said transistor is rendered conductive in order to provide a degenerative selfbias for said transistor further to prevent driving of said transistor into saturation as the input signals at said first frequency increase in amplitude above said predetermined value.

5. The combination according to claim 4 wherein the energy storage device provides a back-bias to the emitter of said transistor.

6. A frequency doubling circuit including in combination:

a source of signals at a first frequency, said signals being subject to varying amplitude;

first and second voltage supply terminals adapted to be connected across a source of DC potential;

a resonant circuit tuned to a frequency which is double said first frequency;

a first transistor having base, collector and emitter electrodes, the collector being coupled through said resonant circuit to said first voltage supply terminal;

circuit means coupling the emitter of said transistor with said second voltage supply terminal;

a second transistor having collector, base and emitter electrodes;

resistance means coupling the emitter-collector path of said second transistor with said first voltage supply terminal;

semiconductor diode means coupling the emitter-collector path of said second transistor with said second voltage supply terminal;

means coupling the emitter-collector path of said second transistor with the base of said first transistor; and

means coupling said source of signals with the base of said second transistor, said semiconductor diode means being poled in the forward current conducting direction with respect to the base-emitter junction of said first transistor for forward biasing said first transistor into conduction and providing logarithmic compression of signals with an amplitude in excess of the forward breakdown voltage of said semiconductor diode means for preventing said first transistor from being driven to saturation.

7. The combination according to claim 6 wherein said diode means includes a plurality of semiconductor diode junctions the polarity of which is such that current flowing therethrough in the forward current conducting direction produces a forward biasing potential for said first transistor.

8. The combination according to claim 7 wherein said plurality of semiconductor diode junctions are connected in series between the emitter of said second transistor and said second voltage supply terminal, said resistance means is connected between the collector of the second transistor and the first voltage supply terminal, and the emitter of said second transistor is connected with the base of said first transistor.

9. The combination according to claim 7 wherein the semiconductor junctions are formed of a plurality of integrated circuit transistors, having the collector-emitter paths thereof connected in series, with the base of each of the plurality of transistors being connected in common to its collec- [01.

10. The combination according to claim 9 further including an energy storage device, said energy storage device being connected at a junction between the emitter of said first transistor and said second voltage supply terminal, so that the emitter of said first transistor is back-biased by the potential stored in said energy storage device to further prevent said first transistor from being driven into saturation.

11. The combination according to claim 10 further including output means connected to said junction for indicating the presence of output signals of a predetermined magnitude whenever said energy storage device is caused to store a predetermined amount of energy.

12. The combination according to claim 10 wherein said energy storage device includes a resistance/capacitance parallel circuit having a capacitor and second resistor connected in parallel between the emitter of said first transistor and said second voltage supply terminal, with said capacitor being rapidly charged by the peaks of the signal present on the emitter of said first transistor and with said second resistor providing a relatively long discharge time for said capacitor, so that a DC voltage indicative of the peaks of the signal ob- 

2. The combination according to claim 1 wherein said semiconductor diode means includes a plurality of semiconductor diode junctions connected in series between the base of said transistor and said second voltage supply terminal, with said semiconductor diode junctions being forward biased by the peaks of signals at said first frequency which are in excess of the forward breakdown voltage of said semiconductor diode junctions interconnected between the base of said transistor and said second voltage supply terminal.
 3. The combination according to claim 2 further including a resistor coupled to the base of said transistor in parallel with at least one of said semiconductor diode junctions.
 4. The combination according to claim 1 further including an energy storage device connected between the emitter of said transistor and said second voltage supply terminal, said energy storage device storing energy during the periods when said transistor is rendered conductive in order to provide a degenerative self-bias for said transistor further to prevent driving of said transistor into saturation as the input signals at said first frequency increase in amplitude above said predetermined value.
 5. The combination according to claim 4 wherein the energy storage device provides a back-bias to the emitter of said transistor.
 6. A frequency doubling circuit including in combination: a source of signals at a first frequency, said signals being subject to varying amplitude; first and second voltage supply terminals adapted to be connected across a source of DC potential; a resonant circuit tuned to a frequency which is double said first frequency; a first transistor having base, collector and emitter electrodes, the collector being coupled through said resonant circuit to said first voltage supply terminal; circuit means coupling the emitter of said transistor with said second voltage supply terminal; a second transistor having collector, base and emitter electrodes; resistance means coupling the emitter-collector path of said second transistor with said first voltage supply terminal; semiconductor diode means coupling the emitter-collector path of said second transistor with said second voltage supply terminal; means coupling the emitter-collector path of said second transistor with the base of said first transistor; and means coupling said source of signals with the base of said second transistor, said semiconductor diode means being poled in the forward current conducting direction with respect to the base-emitter junction of said first traNsistor for forward biasing said first transistor into conduction and providing logarithmic compression of signals with an amplitude in excess of the forward breakdown voltage of said semiconductor diode means for preventing said first transistor from being driven to saturation.
 7. The combination according to claim 6 wherein said diode means includes a plurality of semiconductor diode junctions the polarity of which is such that current flowing therethrough in the forward current conducting direction produces a forward biasing potential for said first transistor.
 8. The combination according to claim 7 wherein said plurality of semiconductor diode junctions are connected in series between the emitter of said second transistor and said second voltage supply terminal, said resistance means is connected between the collector of the second transistor and the first voltage supply terminal, and the emitter of said second transistor is connected with the base of said first transistor.
 9. The combination according to claim 7 wherein the semiconductor junctions are formed of a plurality of integrated circuit transistors, having the collector-emitter paths thereof connected in series, with the base of each of the plurality of transistors being connected in common to its collector.
 10. The combination according to claim 9 further including an energy storage device, said energy storage device being connected at a junction between the emitter of said first transistor and said second voltage supply terminal, so that the emitter of said first transistor is back-biased by the potential stored in said energy storage device to further prevent said first transistor from being driven into saturation.
 11. The combination according to claim 10 further including output means connected to said junction for indicating the presence of output signals of a predetermined magnitude whenever said energy storage device is caused to store a predetermined amount of energy.
 12. The combination according to claim 10 wherein said energy storage device includes a resistance/capacitance parallel circuit having a capacitor and second resistor connected in parallel between the emitter of said first transistor and said second voltage supply terminal, with said capacitor being rapidly charged by the peaks of the signal present on the emitter of said first transistor and with said second resistor providing a relatively long discharge time for said capacitor, so that a DC voltage indicative of the peaks of the signal obtained from the emitter of said first transistor is applied to the emitter of said first transistor by said capacitor. 